(1) Field of the Invention
The invention relates to the fabrication of semiconductor circuit devices, and, more particularly, to a method of avoiding copper line damages that are associated with copper line Chemical Mechanical Polishing (CMP).
(2) Description of the Prior Art
The present invention relates to the creation of conductive lines and vias that provide the interconnection of integrated circuits in semiconductor devices and/or the interconnections in a multilayer substrate on which semiconductor device(s) are mounted. The present invention specifically relates to the fabrication of conductive lines and vias by a process known as damascene.
The Damascene process has been demonstrated on a number of applications. The most commonly applied process is first metal or local interconnects. Some early Damascene structures have been achieved using Reactive Ion Etching (RIE) but Chemical Mechanical Planarization (CMP) is used exclusively today. Metal interconnects using Damascene of copper and of aluminum is also being explored.
U.S. Pat. No. 5,614,765 teaches that, in fabricating very and ultra large-scale integration (VLSI and ULSI) circuits with the dual damascene process, an insulating or dielectric material, such as silicon oxide, of a semiconductor device is patterned with several thousand openings for the conductive lines and vias. These openings are filled at the same time with metal, such as aluminum or copper, and serve to interconnect the active and/or passive elements of the integrated circuit. The dual damascene process also is used for forming the multilevel conductive lines of metal, such as copper, in the insulating layers, such as polyimide, of multi-layer substrates on which semiconductor devices are mounted.
Damascene therefore is an interconnection fabrication process in which grooves are formed in an insulating layer and filled with metal to form the conductive lines. Dual damascene is a multi-level interconnection process in which, in-addition to forming the grooves of single damascene, conductive via openings are also formed. In the standard dual damascene process, the insulating layer is coated with a photoresist which is exposed through a first mask with an image pattern of the via openings, the pattern is anisotropically etched in the upper half of the insulating layer. The photoresist now is exposed through a second mask with an image pattern of the conductive line openings, after being aligned with the first mask pattern to encompass the via openings. In anisotropically etching the openings for the conductive lines in the upper half of the insulating material, the via openings already present in the upper half are simultaneously etched and replicated in the lower half of the insulating material. After the etching is complete, both the vias and line openings are filled with metal. Dual damascene is an improvement over single damascene because it permits the filling of both the conductive grooves and vias with metal at the same time, thereby eliminating process steps. Although this standard damascene process offers advantages over other processes for forming interconnections, it has a number of disadvantages. It requires two masking steps to form the pattern, first for the vias and subsequently for the conductive lines. Furthermore, the edges of the via openings in the lower half of the insulating layer, after the second etching, are poorly defined because of the two etchings. In addition, since alignment of the two masks is critical in order for the pattern for the conductive lines to be over the pattern of the vias, a relatively large tolerance is provided and the vias do not extend the full width of the conductive line.
The application of the Damascene process continues to gain wider acceptance, most notably in the process of copper metalization due to the difficulty of copper dry etch where the Damascene plug penetrates deep in very small, sub-half micron, Ultra Large Scale integrated devices. Recent applications have successfully used copper as a conducting metal line, most notably in the construct of CMOS 6-layer copper metal devices. Even for these applications however, the wolfram plug was still used for contact points in order to avoid damage to the devices.
FIG. 1a shows Prior Art problems encountered when filling a Damascene copper plug 12 with copper 16. The plug 12 can be formed in a dielectric layer 10. A void 14 can develop above the opening of a Damascene plug 12 if the opening is relatively narrow and deep, a design characteristic that becomes more common with smaller semiconductor devices. This void 14 is caused by the difficulty experienced in having deep penetrating flow of the copper within the narrow opening. For a shallow or relatively wide plug 18, FIG. 1b, these problems are not experienced. Void 14 (FIG. 1a) also causes planarization problems during subsequent processing steps and can create a reliability issue.
FIG. 2 shows a Prior Art blanket deposition of metal within the hole 22, hole 22 can be formed in dielectric 20. Where the hole 22 is relatively shallow and wide, no problems of deposition are experienced, see FIG. 2a. This blanket deposition requires polish back, in the absence of polish back problems of shorts between metal lines arises caused by remaining metal on top of the surface. FIG. 2b demonstrates another Prior Art approach where the top 26 of the plug 24 is further extended by overfill. The extension 26 can be obtained by depositing a layer of copper across the surface and applying an etchback to that layer such that copper is left in place around the top of the plug.
In short, Prior Art experiences problems in creating a plug for the Damascene process that provides a reliable connect. In filling deep or narrow holes, problems of metal voids can arise. This in turn causes problems with planarization of subsequent layers that are deposited over the Damascene plug since these layers may now be deposited on a surface of poor planarity.
In overfilling a shallow hole, a polish-back is required in order to avoid shorts by leftover materials between metal lines. Polish-back further complicates the process and adds to the expense incurred while in many instances polishing has to be done in combination with buffing in order to obtain acceptable planarization.
While copper has become important for the creation of multilevel interconnections, copper lines frequently show damage after CMP and clean. This in turn causes problems with planarization of subsequent layers that are deposited over the copper lines since these layers may now be deposited on a surface of poor planarity. Isolated copper lines or copper lines that are adjacent to open fields are susceptible to damage. While the root causes for these damages are at this time not clearly understood, poor copper gap fill together with subsequent problems of etching and planarization are suspected. Where over-polish is required, the problem of damaged copper lines becomes even more severe.
U.S. Pat. No. 5,451,551 (Kishnan et al.) shows a TiW layer over a Cu damascene structure.
U.S. Pat. No. 5,731,245 (Joshi et al.) shows a CuGe hard cap over a Cu plug and CMP process. However, this reference differs from the invention.
U.S. Pat. No. 5,741,626 (Jain et al.) shows a Cu dual damascene structure.
U.S. Pat. No. 5,744,376 (Chan et al.) shows a barrier layer over a Cu interconnect.
U.S. Pat. No. 5,693,563 (Teong) shows a TiN layer over a Cu dual damascene structure.